1. Field of the Invention
The present invention relates to a transistor logic circuit for performing logic operations on a plurality of logic inputs expressed by respective pairs of input differential signals.
2. Description of Prior Art
At present, high-speed transistor logic circuits operating at speeds of the order of several tens of GHz, which are based on elements formed of materials such as gallium arsenide, are becoming used in fields of application such as data communication in which high-speed logic processing is necessary. With one type of such high-speed logic circuit, a plurality of differential transistor pairs (where the term “differential transistor pair” is used herein, unless otherwise indicated, to refer to a pair of field-effect transistors having the source electrodes thereof connected together, with the term field-effect transistor being abbreviated to “FET”) are connected such as to selectively enable a plurality of current paths, in accordance with respective differential signal pairs applied to the gate electrodes of the transistor pairs, to perform a logic operation.
The term “differential signal pair” is used herein to signify a pair of binary signals, one of which is the logic inverse of the other, i.e., which vary in mutually opposite directions between logic high and low potentials (referred to herein as the H and L levels respectively, of that signal pair). The voltage range of such H, L level variation, for any specific differential signal pair, in relation to a circuit reference (ground) potential, will be referred to as the level range of that signal pair. One signal of such a pair will be designated as the non-inverted signal (for example whose H and L levels are considered as the logic “1” and “0” states respectively) and the other as the inverted signal, with each such inverted signal being indicated by a superimposed bar on the signal name, in the appended drawings, and by the suffix “-bar” in the following description.
FIG. 8 shows a prior art example of an AND gate which utilizes a source-coupled logic circuit. This is formed of a current switching section which performs logic operations by switching of current paths, and an output signal generating section which produces an output differential signal pair in response to the switching operations of the current switching section. The AND gate operates on two input differential signal pairs, respectively designated as A, A-bar and B, B-bar (with the level range of the pair B, B-bar being lower than that of the pair A, A-bar) to obtain the output differential signal pair OUT, OUT-bar which express the logic product of the logic inputs expressed by signals A and B. The current switching section is formed of FETs 71 to 74, load resistors 31, 32, and a FET 49 which functions as a current source. The source electrodes of the FETs 71, 72 are connected together, as are the source electrodes of the FETs 73, 74, to form two differential transistor pairs. As shown in FIG. 8, the differential transistor pairs are connected in a multi-stage configuration, with current paths passing through the load resistors 31, 32 respectively and through the multi-stage arrangement of differential transistor pairs, into the current source formed by FET 49, and with the transistor pair 71,72 controlled by the differential signal pair A, A-bar and the transistor pair 73, 74 controlled by the differential signal pair B, B-bar.
The output signal generating section is formed of FETs 33, 34, diodes 35, 36, and FETs 47, 48 which function as respective current sources. The FETs 34, 48 and diode 36 constitute a first source follower circuit, which provides current amplification of the signal appearing at point Q, to produce a final output signal OUT having increased drive capacity, with the corresponding inverse signal OUT-bar being produced by a second source follower circuit formed of the FETs 33, 47 and diode 35. The output differential signal pair OUT, OUT-bar vary in potential in the same directions as for the points P, Q respectively, which will be referred to as the connection points. The output differential signal pair OUT, OUT-bar thus express the logic product of the input signals A and B.
A basic problem of such a prior art logic circuit will be described referring to the timing diagram of FIGS. 9A and 9B. FIG. 9A shows the signal waveforms for the case in which the input differential signal pair A, A-bar undergo logic level transitions between the H and L potentials at identical time points, as also do the input signal pair B, B-bar. FIG. 9B is an expanded view of part of FIG. 9A.
With the circuit of FIG. 8, the following current switching operations are performed on the currents which flow through the differential transistor pairs, in accordance with the voltage levels of the input differential signal pairs, A, A-bar and B, B-bar. When both of the signals A and B are at the H level, then current flows in a first current path via the load resistor 31 and FETs 71, 73. In that condition, designating the Vdd potential of the power source as VH as indicated in FIG. 9B, the voltage at the connection point Q will go to a lower value, designated as VL1, as determined by the load resistor value and the level of current in the first current path. In that condition, if the input signal A goes to the L level with input signal B remaining at the H level, then current flows in a second current path via the load resistor 32 and FETs 72, 73. When this occurs, the respective drain-source voltages across each of the FETs 72, 73, 49 will be identical to the drain-source voltages across the FETs 71, 73, 49 when current flows in the first current path, i.e., there is no change in the potential of the point R, the same level of current flows in that path, and so the potential at the connection point P will fall to VL1.
If the input signal B goes to the L level, then irrespective of the level of the input signal A, current flows in a third current path via the load resistor 32 and FETs 74, 49. In this case, current flows through one less FET than for the case of the first or second current path. As a result, a greater value of drain-source bias voltage is developed across each of the FETs 74 and 49, which causes the current passed by the current source FET 49 to increase, by comparison with the level of current of the first or second current paths. The voltage at the connection point P therefore falls to a value VL2, which is lower than VL1, as shown in FIG. 9B.
As a result, even if the pair of input differential signals that are applied to control the differential transistor pair 73, 74 should change in opposite directions at exactly the same time points, there will be a deviation between the respective time points at which current switching occurs for the load resistor 31 and for the load resistor 32. Hence, when a logic level transition of the input signal A occurs, the output signal pair OUT, OUT-bar will not change over between high and low logic level potentials at identical time points.
Specifically, as illustrated in FIG. 9B, there will be an offset voltage amount ΔV between the crossover point of transitions of the output signals OUT, OUT-bar when OUT goes from the L to H level (i.e., from VL1 to VH in FIG. 9B) and the crossover point of these signal transitions when OUT goes from the H to the L level (i.e., from VH to VL2 in FIG. 9B). Since the AND gate is required to operate at a frequency which may be several tens of GHz, such a difference between the waveform rise-time and fall-time characteristics of each signal of the output differential signal pair is a serious problem.